


module Differentiator
    #(
        parameter IWID = 12,
        parameter OWID = 32
    )
    (
        input wire signed [IWID-1:0] i_SigIn,
        input wire i_clk,
        input wire i_rst,
        output reg signed [OWID-1:0] o_diff
    );

    reg [IWID-1:0] Sig_Pre;

    always@(posedge i_clk or posedge i_rst) begin
        if(i_rst) begin
            o_diff<='b0;
            Sig_Pre<='b0;
        end
        else begin
            Sig_Pre<=i_SigIn;
            o_diff<=i_SigIn-Sig_Pre;
        end
    end

endmodule

